Research Article Open Access

Study the Characteristic of P-Type Junction-Less Side Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Lithography

Arash Dehzangi1, Farhad Larki1, E.B. Saion1, Sabar D. Hatagalung2, Makarimi Abdullah3, M.N. Hamidon4 and Jumiah Hassan1
  • 1 Department of Physics, Faculty of Science, University Putra Malaysia, Serdang, Selangor, Malaysia, 43400 Serdang, Selangor, Malaysia
  • 2 School of Materials and Mineral Resources Engineering, University Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia
  • 3 Advanced Materials Research Centre, Sirim Berhad, Lot 34 Jalan Hi-Tech 2/3, Kulim Hi-Tech Park, 09000 Kulim, Kedah, Malaysia
  • 4 Department of Electrical and Electric Engineering, Faculty of Engineering, University of Putra Malaysia, 43400 Serdang, Selangor, Malaysia


Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronic in order to less energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM) and wet etching on p-type Silicon On Insulator (SOI) wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA). Results: We observe in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage falling down the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, make the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased.

American Journal of Applied Sciences
Volume 8 No. 9, 2011, 872-877


Submitted On: 26 March 2011 Published On: 1 August 2011

How to Cite: Dehzangi, A., Larki, F., Saion, E., Hatagalung, S. D., Abdullah, M., Hamidon, M. & Hassan, J. (2011). Study the Characteristic of P-Type Junction-Less Side Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Lithography. American Journal of Applied Sciences, 8(9), 872-877.

  • 7 Citations



  • Silicon Nanowire Transistor (SNWT)
  • Density of State (DoS)
  • electrochemical potential