Research Article Open Access

Hardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate Array

Muhammad Ibn Ibrahimy1, Rezwanul Ahsan1 and Iksannurazmi Bambang Soeroso1
  • 1 Department of Electrical and Computer Engineering, Faculty of Engineering, International Islamic University Malaysia, 53100 Kuala Lumpur, Malaysia


There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (RC) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device.

American Journal of Applied Sciences
Volume 10 No. 5, 2013, 466-477


Submitted On: 14 June 2012 Published On: 28 May 2013

How to Cite: Ibrahimy, M. I., Ahsan, R. & Soeroso, I. B. (2013). Hardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate Array. American Journal of Applied Sciences, 10(5), 466-477.

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  • Binary Coded Decimal Adder
  • Carry Look Ahead
  • Ripple Carry
  • Hardware Description Language
  • Field Programmable Gate Array