Research Article Open Access

A Novel Interconnect Structure for Elmore Delay Model with Resistance-Capacitance-Conductance Scheme

Uma Ramadass1, Krishnappriya2, Jebashini Ponnian3 and P. Dhavachelvan1
  • 1 Department of Computer Science, School of Engineering, Pondicherry University, Pondicherry, India
  • 2 Department of Electronics, School of Engineering, Pondicherry University, Pondicherry, India
  • 3 Department of Electrical and Electronics, Infrastructure University Kualalumpur Kajang, Malaysia

Abstract

In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The RCG model attains quick steady state condition and the accuracy of the interconnect delay estimates can be improved by deploying the conductance effect. The simulation results shows the proposed interconnect scheme performance is better than the existing in terms of delay, power and the figure of merit. The performance analysis depicts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%. The analysis is validated through extensive simulations on a 250 nm CMOS technology.

American Journal of Applied Sciences
Volume 10 No. 8, 2013, 881-892

DOI: https://doi.org/10.3844/ajassp.2013.881.892

Submitted On: 12 April 2013 Published On: 24 July 2013

How to Cite: Ramadass, U., Krishnappriya, Ponnian, J. & Dhavachelvan, P. (2013). A Novel Interconnect Structure for Elmore Delay Model with Resistance-Capacitance-Conductance Scheme. American Journal of Applied Sciences, 10(8), 881-892. https://doi.org/10.3844/ajassp.2013.881.892

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Keywords

  • Elmore Delay
  • RCG Interconnect
  • RLC Network
  • Figure of Merit
  • Damping Ratio