Research Article Open Access

FPGA IMPLEMENTATION AND ANALYSIS OF IMPULSE NOISE REDUCTION IN IMAGES

P. Thirumurugan1, S. Sasikumar2 and C. Sugapriya3
  • 1 Department of Electronics and Communication, PSNA College of Engineering and Technology, Tamil Nadu- 624622, India
  • 2 Department of Electronics and Communication, RMD Engineering College, India
  • 3 Department of Electronics and Communication, RMK Engineering College, India

Abstract

The images are affected by random valued impulse noises during the image capturing and processing stages. In this study, an efficient, high performance and low hardware utilized impulse noise reduction algorithm is presented. This methodology determines the optimum direction pixels through the estimation of standard deviation. The edges in the images are preserved during the process of impulse noise detection and removal stage. The hardware architecture for this design is proposed and its performance is analyzed with different FPGA Processors in terms of slices, LUTs and power consumption. The proposed hardware architecture consumes 1728 gates and power consumption of 159.95 mW. The main motivation behind this research is to design low power impulse noise detection architecture and its real time implementations.

American Journal of Applied Sciences
Volume 11 No. 7, 2014, 1041-1048

DOI: https://doi.org/10.3844/ajassp.2014.1041.1048

Submitted On: 13 January 2014 Published On: 19 April 2014

How to Cite: Thirumurugan, P., Sasikumar, S. & Sugapriya, C. (2014). FPGA IMPLEMENTATION AND ANALYSIS OF IMPULSE NOISE REDUCTION IN IMAGES. American Journal of Applied Sciences, 11(7), 1041-1048. https://doi.org/10.3844/ajassp.2014.1041.1048

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Keywords

  • Impulse Noise Reduction
  • Optimal Detector
  • Power Consumption
  • Edge Detection
  • Image Quality