FAULT AND RELIABILITY ANALYSIS OF CARBON NANO TUBE FET SRAM IN THE PRESENCE OF SINGLE EVENT UPSET
- 1 Electronics and Communication Engineering, P.S.V College of Engineering and Technology, Krishnagiri, Tamilnadu, India
- 2 Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Udumalai road, Pollachi, Tamilnadu, India
Carbon nano tube devices are considered as a better replacement for CMOS technology nowadays due to its decreased sizing and increased performance. Resistive open and bridging faults play vital role in the dynamic fault analysis. These faults are important since the number of interconnects have increased. In this study we discuss the effect of open and bridging defects along with the variation of CNTFET parameters in the presence of Single Event Upsets (SEU). This helps us to analyse and have good comparison of CNTFET and CMOS SRAM faults in the presence of SEU. The analysis of these faults in the presence of SEU helps us to develop new efficient techniques to improve the performance. Presence of single event upset in the presence of these defects was analysed. The fault introduction in CNTFET SRAM showed different fault types for corresponding resistance values. The impact of resistive open defects and bridging defects on CNTFET SRAM in presence of SEU is estimated for different values of resistances compared close to CMOS SRAM.
Copyright: © 2014 T. R. Rajalakshmi and R. Sudhakar. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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- SRAM Carbon Nano Tube FET
- Single Event Upset
- Resistive Open Faults
- Bridging Faults