Research Article Open Access

AREA EFFICIENT DISTRIBUTED ARITHMETIC DISCRETE COSINE TRANSFORM USING MODIFIED WALLACE TREE MULTIPLIER

R. P. Meenaakshi Sundari1, R. Anita2 and V. Venkateshwaran1
  • 1 Department of Electronics and Communication Engineering, Sasurie College of Engineering, Vijayamangalam, Tamilnadu, India
  • 2 Department of Electrical and Electronics Engineering, Institute of Road and Transport Technology, Erode, Tamilnadu, India

Abstract

In this study by using the modified Wallace tree multiplier, an error compensated adder tree is constructed in order to round off truncation errors and to obtain high through put discrete cosine transform design. Peak Signal to Noise Ratio (PSNR) is met efficiently since modified Wallace Tree method is an efficient, hardware implementable digital circuit that multiplies two integers resulting an output with reduced delays and errors. Nearly 6% of delays and around 1% of gate counts are reduced. The number of look up tables consumed is 2% lesser than that of the previous multipliers. Thus an area efficient discrete cosine transform is built to achieve high throughput with minimum gate counts and delays for the required Peak Signal to Noise Ratio when compared to the existing DCT’s.

American Journal of Applied Sciences
Volume 11 No. 2, 2014, 180-188

DOI: https://doi.org/10.3844/ajassp.2014.180.188

Submitted On: 15 March 2013 Published On: 19 December 2013

How to Cite: Sundari, R. P. M., Anita, R. & Venkateshwaran, V. (2014). AREA EFFICIENT DISTRIBUTED ARITHMETIC DISCRETE COSINE TRANSFORM USING MODIFIED WALLACE TREE MULTIPLIER. American Journal of Applied Sciences, 11(2), 180-188. https://doi.org/10.3844/ajassp.2014.180.188

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Keywords

  • 2-D Discrete Cosine Transform
  • Error Compensated Adder Tree (ECAT)
  • Read Only Memory (ROM)
  • New Distributed Arithmetic (NEDA)