Research Article Open Access

A Novel Reconfigurable Execution Core for Merged DSP Microcontroller

A. K. Rath and P. K. Meher

Abstract

The study presents an execution core which can be reconfigured either for calculation of digital convolution or for computation of discrete orthogonal transform by appropriate local buffer initialization of processing cells. It is shown that the data flow pattern can be changed by a single bit control signal. The proposed core can be connected to port 1 of Intel 8051 to derive the necessary control signals for reconfiguration. The core can be used as a pluggable module with existing microcontroller when DSP algorithms are required to be implemented. Using such execution core the computational load of the processor can be significantly reduced as the math-intensive components of the DSP algorithm is relegated to the execution core. The use of such pipelined core will not only caters to the need of real-time performance, but also it will facilitate scalability, reusability and flexibility for wide varieties of DSP functionalities.

Journal of Computer Science
Volume 3 No. 10, 2007, 803-809

DOI: https://doi.org/10.3844/jcssp.2007.803.809

Submitted On: 13 October 2007 Published On: 31 October 2007

How to Cite: Rath, A. K. & Meher, P. K. (2007). A Novel Reconfigurable Execution Core for Merged DSP Microcontroller . Journal of Computer Science, 3(10), 803-809. https://doi.org/10.3844/jcssp.2007.803.809

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Keywords

  • Digital Signal Processor
  • microcontroller
  • merged architecture
  • embedded system
  • corebased DSP