Research Article Open Access

Design of Low- Power High-Speed Error Tolerant Shift and Add Multiplier

K. N. Vijeyakumar, V. Sumathy, Sriram Komanduri and C. Chrisjin Gnana Suji

Abstract

Problem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder cells and bypassing adder for zero bit values of the multiplier constant. The architecture makes use of down counter for tracking shift of partial products and multiplier bits. Results: When compared to the conventional architecture the simulation results for 8×8 multiplier shows that the proposed design reduces power consumption by 23.8% and delay by 35.6%. Conclusion: Enhanced performance of the proposed Error Tolerant shift and add multiplier in terms of power and delay makes it suitable for portable image processing applications where minimum percentage of error is tolerable.

Journal of Computer Science
Volume 7 No. 12, 2011, 1839-1845

DOI: https://doi.org/10.3844/jcssp.2011.1839.1845

Submitted On: 19 July 2011 Published On: 18 October 2011

How to Cite: Vijeyakumar, K. N., Sumathy, V., Komanduri, S. & Suji, C. C. G. (2011). Design of Low- Power High-Speed Error Tolerant Shift and Add Multiplier. Journal of Computer Science, 7(12), 1839-1845. https://doi.org/10.3844/jcssp.2011.1839.1845

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Keywords

  • High speed arithmetic
  • error tolerant technique
  • down counter
  • Partial Product (PP)
  • image processing
  • power dissipation
  • Digital Signal Processing (DSP)
  • Least Significant Bit (LSB)
  • adder cells