Research Article Open Access

A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits

D. Jayanthi1 and M. Rajaram2
  • 1 Sona College of Technology Salem-636 005, India
  • 2 Anna University of Technology, India


Problem statement: Recent research in asynchronous design technique is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low power, the growing challenges of predicting the increasing impact of wire load and delay and the performance penalty associated with supporting communication between different clock domains Asynchronous is binary signals, but there is no common or discrete time. Instead the circuits use handshaking between their components in order to perform the needed synchronization, communication and sequencing of operations. This difference gives asynchronous circuits’ inherent properties in the areas of lower power consumption, higher operating speed and robustness toward variations in supply voltage, temperature and fabrication process parameters, less emission of electromagnetic noise, better modularity, no clock distribution and clock skew problems. Low power consumption seems to be one of the most promising directions and the design reported in this study is one of these examples. Approach: In this study provide different solutions to these problems that the spectrum of existing asynchronous design technique support. It focuses on technique for fine grain two dimensional pipelining that yield ultra high speed at normal power supplies and very low energy at reduced power supplies. The new templates that provide significant performance improvements in quasi delay insensitivity. The key idea is to reduce the complexity of internal circuitry by intelligently reducing concurrency and using an additional wire for communication between pipeline stages. Results: In this study, Quasi Delay Insensitive RSPCHB template has been proposed to enhance the performance is faster with a maximum throughput of 970MHz than the previously designed system. Conclusion: The proposed model has been tested using HSPICE. The authors believe that the proposed design will provide a platform for designing high speed, low power digital circuits such as pipelined multiplier implemented in any application of digital signal processors.

Journal of Computer Science
Volume 8 No. 7, 2012, 1114-1122


Submitted On: 3 March 2012 Published On: 7 June 2012

How to Cite: Jayanthi, D. & Rajaram, M. (2012). A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits. Journal of Computer Science, 8(7), 1114-1122.

  • 0 Citations



  • Asynchronous channel
  • handshake protocol
  • QDI templates
  • reduced stack pre-charged half buffer
  • asynchronous pipeline adder