Research Article Open Access

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

T. S. Karthik and V. Jawahar Senthil Kumar

Abstract

Problem statement: In any multimedia processor, controller may consume most of the on-chip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications are made with software reference implementation. The whole system is implemented in 0.18 μm CMOS technology, where an input reference clock to an outgoing data clock monitors and true locking is initialized with 50% duty cycle correction. Results: From the measurement result of DLL operation, the output clock jitter is analyzed. Power consumption of DLL including large size output buffer is about few mW. Conclusion: The great challenge in this implementation is communication bandwidth, has brought to process variation and power state reduction techniques. In addition, inefficiency of computing capacity and simultaneous switching noise is reduced in the real time applications.

Journal of Computer Science
Volume 8 No. 3, 2012, 305-309

DOI: https://doi.org/10.3844/jcssp.2012.305.309

Submitted On: 24 November 2011 Published On: 6 January 2012

How to Cite: Karthik, T. S. & Kumar, V. J. S. (2012). High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction. Journal of Computer Science, 8(3), 305-309. https://doi.org/10.3844/jcssp.2012.305.309

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Keywords

  • Delay locked loop
  • voltage control delay line
  • coarse lock detector
  • process variation
  • simultaneous switching noise