Research Article Open Access

HIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMS

C. G. Ravichandran1 and S. Venkateshbabu2
  • 1 Anna University, India
  • 2 , India

Abstract

This study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing extraneous glitches and transitions. It is an approach for the design and comparison of 16-bit adders for low-power signal processing applications. Simulation and Synthesis results show that the proposed adder outperforms the conventional adders in terms of power consumption, delay and transistor count.

Journal of Computer Science
Volume 10 No. 5, 2014, 737-744

DOI: https://doi.org/10.3844/jcssp.2014.737.744

Submitted On: 14 April 2013 Published On: 30 December 2013

How to Cite: Ravichandran, C. G. & Venkateshbabu, S. (2014). HIGH SPEED PROBABILISTIC ADDER FOR SIGNAL PROCESSING SUBSYSTEMS. Journal of Computer Science, 10(5), 737-744. https://doi.org/10.3844/jcssp.2014.737.744

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Keywords

  • Power Delay Product
  • Signal Processing
  • Low Power Design
  • Probabilistic Approach
  • Acceptable Accuracy