@article {10.3844/ajassp.2008.136.141,
article_type = {journal},
title = {Design of Low Phase Noise SIPC based Complementary LC-QVCO for IEEE 802.11a Application},
author = {Ramiah, Harikrishnan and Azni Zulkifli, Tun Zainal},
volume = {5},
year = {2008},
month = {Feb},
pages = {136-141},
doi = {10.3844/ajassp.2008.136.141},
url = {https://thescipub.com/abstract/ajassp.2008.136.141},
abstract = {The paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in a complementary architecture, which is usually preferred in low-power applications as it exploits ≈50% bias current reduction with double efficiency compared to the structure with single coupled, when operating in the current-limited regime. A stacked spiral inductor exhibiting a Q factor of 5.8, with pMOS based depletion mode varactor of 32% in tuning range, corresponding to 3.2-3.6GHz of tuning frequency, is implemented in 0.18µm CMOS technology. The phase noise of the SIPC QVCO architecture simulated at 1MHz of offset frequency is indicated to be -114.3dBc/Hz, while dissipating 11.0mW of core circuit power.},
journal = {American Journal of Applied Sciences},
publisher = {Science Publications}
}