@article {10.3844/ajassp.2011.1176.1181,
article_type = {journal},
title = {Single Core Hardware Module to Implement Boolean Function Classification Techniques},
author = {Marufuzzaman, Mohd. and Mamun, Md. and Hashim, Fazidah Hanim and Rahman, Labonnah F.},
volume = {8},
year = {2011},
month = {Oct},
pages = {1176-1181},
doi = {10.3844/ajassp.2011.1176.1181},
url = {https://thescipub.com/abstract/ajassp.2011.1176.1181},
abstract = {Problem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was performed by incorporating Boolean function classification into Huffman coding. This allows compression that was more efficient because the data had been categorized and simplified before the encoding was done. Simulation, timing analysis and circuit synthesis were commenced to verify the functionality and performance of the designated circuits which supports the practicality, advantages and effectiveness of the proposed single core hardware implementation. Results: The result shows a higher compression ratio. The average compression ratio was 25-37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz. Conclusion: The hardware implementation demonstrated complete, correct functionality and met all	the initial system requirements. },
journal = {American Journal of Applied Sciences},
publisher = {Science Publications}
}