TY  - JOUR
AU  - Sampath, Karthik Thirumalai 
AU  - Veerabadran, Jawahar Senthil Kumar 
PY  - 2013
TI  - Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-FPGA Systems
JF  - American Journal of Applied Sciences
VL  - 10
IS  - 12
DO  - 10.3844/ajassp.2013.1604.1615
UR  - https://thescipub.com/abstract/ajassp.2013.1604.1615
AB  - In this age of scientific computing, the experiment models and evaluation is a commonly employed rendition of the simulation methods. In addition to the optimality, the methods which depict underlying uncertainty in process variation. It is accomplished by adjusting number of samples on delay and wire width. Here addresses the thermal profile, if temperature gradually increases, also reduce worst case clock skew under thermal variation. Under the SSTA analysis the mean delay is 6.2 to 5.2% and standard deviation from 7.5 to 7.6% is reduced. Therefore the overall performance measure in storage and the run time is very low. Extensive simulation studies show that of how does one accurately and efficiently post-process stochastic simulation fields and how does one effectively and succinctly convey the results.