@article {10.3844/ajassp.2014.69.73,
article_type = {journal},
title = {AN IMPROVED DESIGN OF REVERSIBLE BINARY TO BINARY CODED DECIMAL CONVERTER FOR BINARY CODED DECIMAL MULTIPLICATION},
author = {Murugesan, Praveena and Keppanagounder, Thanushkodi},
volume = {11},
year = {2013},
month = {Nov},
pages = {69-73},
doi = {10.3844/ajassp.2014.69.73},
url = {https://thescipub.com/abstract/ajassp.2014.69.73},
abstract = {Reversible logic gates under ideal conditions produce zero power dissipation. This factor highlights the usage of these gates in optical computing, low power CMOS design, quantum optics and quantum computing. The growth of decimal arithmetic in various applications as stressed the need to propose the study on reversible binary to BCD converter which plays a greater role in decimal multiplication for providing faster results. The different parameters such as gate count,garbage output and constant input are more optimized in the proposed fixed bit binary to binary coded decimal converter than the existing design.},
journal = {American Journal of Applied Sciences},
publisher = {Science Publications}
}