@article {10.3844/ajassp.2014.883.887,
article_type = {journal},
title = {A RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESS},
author = {Yasodha, T. and Raglend, I. Jacob and Jeyanthi, K. Meena Alias},
volume = {11},
year = {2014},
month = {Mar},
pages = {883-887},
doi = {10.3844/ajassp.2014.883.887},
url = {https://thescipub.com/abstract/ajassp.2014.883.887},
abstract = {A novel channel based rescheduling scheme for modern turbo convolution code is proposed by the inclusion of suboptimal and low-complex max-log-MAP algorithm. Demands for dedicated custom solutions in mobile communications and its related applications leads to a reconfigurable architecture for Turbo convolution code. This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme in MIMO-High Speed Downlink Packet Access (MIMO-HSDPA). To attain effective performance close to shannon limit in a multi channel system, flexible reconfigurable architecture is realized with 28 nm cyclone V GX 5CGXFC5C6 FPGA. We achieved throughput of 13.5 Mbps compared with the conventional HSDPA standards while consuming 53 mW.},
journal = {American Journal of Applied Sciences},
publisher = {Science Publications}
}