TY - JOUR AU - Yasodha, T. AU - Raglend, I. Jacob AU - Jeyanthi, K. Meena Alias PY - 2014 TI - A RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESS JF - American Journal of Applied Sciences VL - 11 IS - 6 DO - 10.3844/ajassp.2014.883.887 UR - https://thescipub.com/abstract/ajassp.2014.883.887 AB - A novel channel based rescheduling scheme for modern turbo convolution code is proposed by the inclusion of suboptimal and low-complex max-log-MAP algorithm. Demands for dedicated custom solutions in mobile communications and its related applications leads to a reconfigurable architecture for Turbo convolution code. This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme in MIMO-High Speed Downlink Packet Access (MIMO-HSDPA). To attain effective performance close to shannon limit in a multi channel system, flexible reconfigurable architecture is realized with 28 nm cyclone V GX 5CGXFC5C6 FPGA. We achieved throughput of 13.5 Mbps compared with the conventional HSDPA standards while consuming 53 mW.