Research Article Open Access

A New Efficient-Silicon Area MDAC Synapse

Zied Gafsi, Nejib Hassen, Mongia Mhiri and Kamel Besbes

Abstract

Using the binary representation ΣiDi2i in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named Arithmetic MDAC (AMDAC) is designed. It functions with a new representation based on arithmetic progressions. Using the AMS CMOS 0.35μm technology the silicon area is reduced by a factor of 40%.

American Journal of Applied Sciences
Volume 4 No. 6, 2007, 378-385

DOI: https://doi.org/10.3844/ajassp.2007.378.385

Submitted On: 3 January 2007 Published On: 30 June 2007

How to Cite: Gafsi, Z., Hassen, N., Mhiri, M. & Besbes, K. (2007). A New Efficient-Silicon Area MDAC Synapse. American Journal of Applied Sciences, 4(6), 378-385. https://doi.org/10.3844/ajassp.2007.378.385

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Keywords

  • MDAC
  • binary representation
  • efficient silicon area