Design of Low Phase Noise SIPC based Complementary LC-QVCO for IEEE 802.11a Application
The paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in a complementary architecture, which is usually preferred in low-power applications as it exploits ≈50% bias current reduction with double efficiency compared to the structure with single coupled, when operating in the current-limited regime. A stacked spiral inductor exhibiting a Q factor of 5.8, with pMOS based depletion mode varactor of 32% in tuning range, corresponding to 3.2-3.6GHz of tuning frequency, is implemented in 0.18µm CMOS technology. The phase noise of the SIPC QVCO architecture simulated at 1MHz of offset frequency is indicated to be -114.3dBc/Hz, while dissipating 11.0mW of core circuit power.
Copyright: © 2008 Harikrishnan Ramiah and Tun Zainal Azni Zulkifli. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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- Phase noise
- pMOS varactor
- Quadrature voltage controlled oscillator (QVCO)
- Source injection parallel coupled VCO (SIPC-QVCO)
- Stacked spiral inductor