Research Article Open Access

Design of Low Phase Noise SIPC based Complementary LC-QVCO for IEEE 802.11a Application

Harikrishnan Ramiah and Tun Zainal Azni Zulkifli

Abstract

The paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in a complementary architecture, which is usually preferred in low-power applications as it exploits ≈50% bias current reduction with double efficiency compared to the structure with single coupled, when operating in the current-limited regime. A stacked spiral inductor exhibiting a Q factor of 5.8, with pMOS based depletion mode varactor of 32% in tuning range, corresponding to 3.2-3.6GHz of tuning frequency, is implemented in 0.18µm CMOS technology. The phase noise of the SIPC QVCO architecture simulated at 1MHz of offset frequency is indicated to be -114.3dBc/Hz, while dissipating 11.0mW of core circuit power.

American Journal of Applied Sciences
Volume 5 No. 2, 2008, 136-141

DOI: https://doi.org/10.3844/ajassp.2008.136.141

Submitted On: 17 March 2007 Published On: 28 February 2008

How to Cite: Ramiah, H. & Azni Zulkifli, T. Z. (2008). Design of Low Phase Noise SIPC based Complementary LC-QVCO for IEEE 802.11a Application. American Journal of Applied Sciences, 5(2), 136-141. https://doi.org/10.3844/ajassp.2008.136.141

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Keywords

  • Phase noise
  • pMOS varactor
  • Quadrature voltage controlled oscillator (QVCO)
  • Source injection parallel coupled VCO (SIPC-QVCO)
  • Stacked spiral inductor