Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-FPGA Systems
- 1 Department of Electronics and Communication Engineering, Faculty of Information and Communication Engineering, College of Engineering-Guindy, Anna University, Chennai-600025, India
In this age of scientific computing, the experiment models and evaluation is a commonly employed rendition of the simulation methods. In addition to the optimality, the methods which depict underlying uncertainty in process variation. It is accomplished by adjusting number of samples on delay and wire width. Here addresses the thermal profile, if temperature gradually increases, also reduce worst case clock skew under thermal variation. Under the SSTA analysis the mean delay is 6.2 to 5.2% and standard deviation from 7.5 to 7.6% is reduced. Therefore the overall performance measure in storage and the run time is very low. Extensive simulation studies show that of how does one accurately and efficiently post-process stochastic simulation fields and how does one effectively and succinctly convey the results.
Copyright: © 2013 Karthik Thirumalai Sampath and Jawahar Senthil Kumar Veerabadran. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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- Clock tree DLL
- Directionless Routing
- Interconnect Uncertainty
- Temperature Aware