Research Article Open Access

An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware

Abdellatif Mtibaa, Abdessalem B. Abdelali, Lotfi Boussaid and Elbey Bourennane

Abstract

In this study we propose a framework and a combined temporal partitioning and design space exploration method for run time reconfigurable processors. Our objective is to help designers to implement an algorithm in limited FPGA area resources while respecting the execution time constraint. The algorithm to be implemented is represented by a task graph with different implementation alternatives (design points) for each task. We study the effect of hardware resources limitation in the choice of the algorithm implementation design point. The proposed method is based on an heuristic technique which consists on combining temporal partitioning and task design points selection to obtain solutions that satisfy the imposed constraints.

Journal of Computer Science
Volume 2 No. 5, 2006, 422-430

DOI: https://doi.org/10.3844/jcssp.2006.422.430

Submitted On: 20 February 2006 Published On: 31 May 2006

How to Cite: Mtibaa, A., Abdelali, A. B., Boussaid, L. & Bourennane, E. (2006). An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware. Journal of Computer Science, 2(5), 422-430. https://doi.org/10.3844/jcssp.2006.422.430

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Keywords

  • Reconfigurable hardware
  • run time reconfiguration
  • time partitioning
  • design points