Research Article Open Access

Delay and Power Reduction in New Routing Fabrics

S. Vijayakumar1, J. Sundararajan2, P. Kumar3 and K. Nithya4
  • 1 Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, TN, India
  • 2 Paavai College of Technology, Namakkal, TN, India
  • 3 Department of Electronics and Communication Engineering, K.S. Rangasamy College of Technology, Tiruchengode, TN, India
  • 4 Department of Electronics and Communication Engineering, Paavai College of Engineering, Namakkal, TN, India

Abstract

In this study we created a new routing fabric for reducing power and delay. The power consumed in a FPGA core consists of both static and dynamic components. Static power contributes only 10% of the total power consumed in a FPGA. On the other hand, dynamic power contributes over 90% of the total power consumed and it is the main source for their power inefficiency. By reducing net length and/or programming overhead the power consumption reduced. Routed net length reduced by using short intersects segments in the routing channels. By decreasing the switch box and/or connection box flexibilities programming overhead reduced. In this study ,we concentrated on achieving 1.80 times lower consumption of dynamic power and 1.50 times less significant average net delays by re-architecting the programmable routing fabrics such that both routed net lengths and programming overhead reduced without adversely affecting delay.

American Journal of Applied Sciences
Volume 10 No. 12, 2013, 1537-1545

DOI: https://doi.org/10.3844/ajassp.2013.1537.1545

Submitted On: 15 July 2013 Published On: 23 October 2013

How to Cite: Vijayakumar, S., Sundararajan, J., Kumar, P. & Nithya, K. (2013). Delay and Power Reduction in New Routing Fabrics. American Journal of Applied Sciences, 10(12), 1537-1545. https://doi.org/10.3844/ajassp.2013.1537.1545

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Keywords

  • Routing Fabrics Logic Block
  • Routed Segment
  • Glitches
  • Dynamic Power
  • Average Net Delay