Delay and Power Reduction in New Routing Fabrics
- 1 Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, TN, India
- 2 Paavai College of Technology, Namakkal, TN, India
- 3 Department of Electronics and Communication Engineering, K.S. Rangasamy College of Technology, Tiruchengode, TN, India
- 4 Department of Electronics and Communication Engineering, Paavai College of Engineering, Namakkal, TN, India
In this study we created a new routing fabric for reducing power and delay. The power consumed in a FPGA core consists of both static and dynamic components. Static power contributes only 10% of the total power consumed in a FPGA. On the other hand, dynamic power contributes over 90% of the total power consumed and it is the main source for their power inefficiency. By reducing net length and/or programming overhead the power consumption reduced. Routed net length reduced by using short intersects segments in the routing channels. By decreasing the switch box and/or connection box flexibilities programming overhead reduced. In this study ,we concentrated on achieving 1.80 times lower consumption of dynamic power and 1.50 times less significant average net delays by re-architecting the programmable routing fabrics such that both routed net lengths and programming overhead reduced without adversely affecting delay.
Copyright: © 2013 S. Vijayakumar, J. Sundararajan, P. Kumar and K. Nithya. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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- Routing Fabrics Logic Block
- Routed Segment
- Dynamic Power
- Average Net Delay